1. Field of the Invention
The present invention relates to a cell structure of dynamic RAM (i.e. DRAM), for example, more specifically, a STC (Stacked Capacitor)-type semiconductor storage device in which a memory cell capacitor is formed above a bit line so as to be self-aligned with the bit line, and relates to a manufacturing method thereof.
2. Description of the Related Art
Recently, a semiconductor storage device, particularly, a DRAM has been integrated greatly. Accordingly, a percentage of a unit storage element is showing a tendency to further increase. For this reason, a three-dimensional memory cell capacitor and a three-dimensional memory cell transistor are indispensable for obtaining enough capacity (not less than 20 fF) to read/write. As a result, a cell structure using a trench-type capacitor or STC-type capacitor is generally used.
In addition, in the cell using the STC-type capacitor, a technique for forming a memory cell capacitor so that it is self-aligned with a bit line is important to greater-scale integration. As a method of manufacturing the conventional STC-type capacitor, a memory cell is suggested as described in, for example, M. Fukumoto et al., “Stacked capacitor cell technology for 16 M DRAM using double self aligned contacts”, ESSDERC 90, pp. 461-464, 1990. FIGS. 13 through 15 show its example.
FIG. 13 shows a plan view of the memory cell. In FIG. 13, 201 is a channel region, 202 is a gate electrode pattern, 203 is a bit line contact, 204 is a bit line pattern, 205 is a storage node contact pattern, and 206 is a storage node electrode pattern.
FIGS. 14A through 14C show manufacturing steps of a cross-sectional view taken along line 14—14 in FIG. 13. As shown in FIG. 14A, an element separating oxide film 52, a MOS transistor for transmitting data, not shown, a first inter-layer insulating film 53, a bit line contact, not shown, a bit line 54, and a second inter-layer insulating film 55 made of BPSG film are formed on a semiconductor substrate 51. Next, a storage node contact 56 which reaches the semiconductor substrate 51 is formed in the first and second inter-layer insulating films 53 and 55 which is located between the bit lines 54—54 by the known lithography method and the RIE (Reactive Ion Etching) method.
Next, as shown in FIG. 14B, an HTO (High Temperature Oxide) film 57 is deposited over the whole surface, and the whole surface is etch-backed by the RIE method. Then, as shown in FIG. 14C, a side wall spacer 58 constituted by the HTO film 57 is formed on the first and second inter-layer insulating films exposed in the storage node contact 56.
If the storage node contact pattern 205 shown in FIG. 13 is not aligned with the bit line pattern 204, the following problems arise. As shown in FIG. 15A, when the storage node contact 56 is formed, the bit line 54 is exposed from the first and second inter-layer insulating films 53 and 55. In this state, as shown in FIG. 15B, the HTO film 57 is deposited on the whole surface, the whole surface is etch-backed by the RIE method. Then, as shown in FIG. 15C, the side wall spacer 58 is formed in the storage node contact 56 so as to be on the bit line 54 and the side wall of the second inter-layer insulating film 55. However, since a part of the bit line 54 is exposed from a gap of the side wall spacer 58, the storage node, not shown, which is formed later and the bit line 54 are short-circuited.
In addition, when the whole surface of the HTO film 57 is etch-backed, since the HTO film 57 and the second inter-layer insulating film 55 are made of silicon oxide, sufficient selectivity cannot be obtained. Therefore, it becomes difficult to control thicknesses of the insulating film on the bit line 54 and the second inter-layer insulating film 55.
Furthermore, when the storage node contact 56 is formed, since a contact opening and a contact gap are minute, it is difficult to form a resist pattern. Moreover, the storage node contact 56 does not have a desired shape, i.e. square shape, and as shown by broken lines in FIG. 13, it has a circular shape. The circular shape has a diameter which is a minimum dimension of the diameter when the storage node contact 56 is inscribed in a square pattern. The contact area decreases, thereby increasing contact resistance. Moreover, since the storage node contact 56 reaches the semiconductor substrate 51, an aspect ratio becomes large. As a result, the yield of the contact opening is not efficient, and thus it is difficult to plug up the storage node.